The entire disclosure of Japanese Patent Application No. 2002-349861 filed on Dec. 2, 2002 and No. 2003-027189 filed on Feb. 4, 2003 including their specifications, claims, drawings and summaries are incorporated herein by reference in its entirety.
1. Field of the Invention
This invention relates to a data holding device and a data holding method and, more particularly, to a data holding device and a data holding method using a nonvolatile memory element.
2. Description of Prior Art
As a data holding circuit for use in a sequential circuit such as a latch circuit, a circuit in which two inverter circuits are connected in a loop is known. Such a data holding circuit, however, can usually hold data only in a volatile manner, and the data are lost when the power source is interrupted. Namely, even when the power source is turned on again, it is impossible to restore the data to a state it was in before the power source was interrupted. Thus, when sequence processing using a latch circuit having such a data holding circuit must be suspended for some reason and the data must be held, the power source must be kept on and accordingly electric power is consumed. When sequence processing is terminated by an accidental power failure or the like, the processing must be restarted from the beginning, resulting in a large loss in time.
To solve the problems, a latch circuit 401 comprising such a data holding circuit described as above and a plurality of ferroelectric capacitors as shown in FIG. 24 (Japanese Patent Laid-Open No. 2001-126469) and a circuit 403 using a ferroelectric capacitor as shown in FIG. 25 (Japanese Patent Laid-Open No. Hei-05-250881) has been proposed.
Using the latch circuit 401 is advantageous since data can be held even when the power source is interrupted.
The latch circuit 401, however, has the following problems. Since the latch circuit 401 comprises a data holding circuit and a plurality of ferroelectric capacitors, a multiplicity of peripheral circuits and control lines for controlling them are necessary in addition to the ferroelectric capacitors. Thus, the circuit area is considerably large as compared with a latch circuit without a ferroelectric capacitor. The latch circuit 401 cannot therefore meet the demand of the industry for improving the integration degree.
Also, the latch circuit 401 requires fine timing control since data are stored in the plurality of ferroelectric capacitors or restored therefrom. Thus, there are severe limitations in designing a circuit. For example, it is necessary to pay attention to the temperature characteristics of the elements for use in the circuit or to provide a temperature compensation circuit.
In the circuit 403 shown in FIG. 25, ferroelectric capacitors connected in series to gate capacitance of field-effect transistors are connected in a flip-flop state. The ferroelectric substance is polarized corresponding to stored data and the threshold voltage of the field-effect transistor is changed depending upon the polarization direction. Since the polarization of the ferroelectric substance is not lost even when the power source is interrupted, the change in the threshold value of the field-effect transistor is maintained.
Then, when the power source is turned on again, the data do not become indefinite but are specified because of the deviation in the threshold value of the field-effect transistors corresponding to the polarization. The data before power off can be thereby restored.
The circuit 403, however, has the following problems. Since the ferroelectric capacitor and the gate capacitance of the field-effect transistor are connected in series, the power source voltage is divided between the ferroelectric capacitor and the gate capacitance.
Thus, when the power source voltage is constant, the voltage applied to the ferroelectric capacitor is reduced, making it difficult to hold data with high reliability. Also, the voltage applied to the gate capacitance of the field-effect transistor is also reduced, the current flowing between the source and drain of the transistor is reduced, making the operation speed of the circuit slower.
The above problems could be solved by increasing the power source voltage. However, this reduces the reliability of the transistor and increases power consumption.
This invention has been made to solve the problems of the conventional circuits and it is, therefore, an object of this invention to provide a data holding device and a data holding method with which data can be held even when the power source is interrupted and the held data can be restored accurately, which do not largely increase the circuit area, and which do not require fine timing control.
Another object of this invention is to provide a high-speed and low-power consumption data holding device which can hold data even when the power source is interrupted, and which can hold data with high reliability.
A data holding device according to this invention comprises a data holding circuit in which data are held by connecting first and second inverter circuits in a loop at the time of latching data, and a nonvolatile memory element which records a nonvolatile state corresponding to data existing in the data holding circuit with one end of the nonvolatile memory element connected to an input node of the first inverter circuit at the time of writing data, and which discharges an electric charge which corresponds to the nonvolatile state recorded in the nonvolatile memory element and which can generate a voltage higher or lower than the threshold voltage of the first inverter circuit at the input node of the first inverter circuit to the input node of the first inverter circuit when the one end of the nonvolatile memory element is connected to the input node of the first inverter circuit and a reading signal is applied to the other end thereof at the time of restoring data, the data holding circuit having a loop switching gate which is interposed between a nonvolatile memory element connecting node defined as a connecting node between the input node of the first inverter circuit and the one end of the nonvolatile memory element, and an output node of the second inverter circuit, and which is on at the time of latching and writing data, and off in applying the reading signal and on after a lapse of a predetermined period of time at the time of restoring data.
A data holding method according to this invention comprises: a step of preparing a data holding device having a data holding circuit in which data are held by connecting first and second inverter circuits in a loop at the time of latching data, and a nonvolatile memory element having an end which is connected to an input node of the first inverter circuit at least at the time of writing and restoring data, the data holding circuit having a loop switching gate interposed between a nonvolatile memory element connecting node defined as a connecting node between the input node of the first inverter circuit and the one end of the nonvolatile memory element, and an output node of the second inverter circuit; a step of recording a nonvolatile state corresponding to data existing in the data holding circuit in the nonvolatile memory element with the one end of the nonvolatile memory element connected to the input node of the first inverter circuit at the time of writing data; and a step of restoring data corresponding to a nonvolatile state recorded in the nonvolatile memory element in the data holding circuit, including the steps of switching off the loop switching gate with the power source of the data holding device on, allowing the nonvolatile memory element to discharge an electric charge which corresponds to the nonvolatile state recorded therein and can generate a voltage higher or lower than the threshold voltage of the first inverter circuit at the input node of the first inverter circuit to the input node of the first inverter circuit by connecting the one end of the nonvolatile memory element to the input node of the first inverter circuit and applying a reading signal to the other end of the nonvolatile memory element, and connecting the first and second inverter circuits in a loop by switching on the loop switching gate after a lapse of a predetermined period of time at the time of restoring data.
A data holding device according to this invention having a data holding circuit in which data are held by connecting two inverter circuits in a loop, comprises: a variable resistance element interposed between a memory node of the data holding circuit and a reference potential; and a nonvolatile memory element for controlling the resistance value of the variable resistance element, wherein a state corresponding to data stored in the data holding circuit is recorded in the nonvolatile memory element, and data corresponding to a state recorded in the nonvolatile memory element are restored in the data holding circuit.
A data holding device according to this invention having a data holding circuit in which data are held by connecting two inverter circuits in a loop, comprises: a variable resistance element interposed between a memory node of the data holding circuit and a reference potential; and a nonvolatile memory element for controlling the resistance value of the variable resistance element, wherein a state corresponding to data at optional point in time stored in the data holding circuit is recorded in the nonvolatile memory element and data corresponding to a state recorded in the nonvolatile memory element is restored in the data holding circuit.
A data holding method according to this invention comprises: a step of preparing a data holding device having a data holding circuit in which data are held by connecting two inverter circuits in a loop, a variable resistance element interposed between a memory node of the data holding circuit and a reference potential, and a nonvolatile memory element for controlling the resistance value of the variable resistance element; a step of automatically writing data in the data holding circuit into the nonvolatile memory element; a step in which the nonvolatile memory element holds the final data in the data holding circuit while the power source of the data holding device is off; and a step of restoring data held in the nonvolatile memory element in the data holding circuit when the power source of the data holding device is restored.
A data holding method according to this invention comprises: a step of preparing a data holding device having a data holding circuit in which data are held by connecting two inverter circuits in a loop, a variable resistance element interposed between a memory node of the data holding circuit and a reference potential, and a nonvolatile memory element for controlling the resistance value of the variable resistance element; a step of writing data, at an optional point in time, in the data holding circuit into the nonvolatile memory element; a step in which the nonvolatile memory element holds data written therein while the power source of the data holding device is off; and a step of restoring data held in the nonvolatile memory element in the data holding circuit when the power source of the data holding device is restored.
Although the features of this invention can be generally described as above, the constitution and details, together with the objects and features, of this invention will be more apparent from the following disclosure in conjunction with appended drawings.